The present invention relates generally to integrated circuit designs, and more particularly to a static random access memory (SRAM) with reduced leakage current.
SRAM, a volatile memory device, provides data storage capability as long as it is supplied with power. As opposed to dynamic random access memory (DRAM), SRAM provides faster and more reliable data storage, and does not need to be refreshed constantly. A standard six-transistor SRAM cell includes a pair of cross-connected inverters and two pass-gate transistors. The inverters are coupled between a power supply node and ground. The pass-gate transistors couple the inverters to a bit line and a complementary bit line, respectively. When the cell is being accessed, the pass-gate transistors are selected to allow the cross-connected inverters to be written into or read from.
Many efforts have been made to reduce the leakage current of SRAM in order to improve its reliability. FIG. 1 schematically illustrates a conventional SRAM cell 100 with the leakage current reduction feature (see, U.S. Pat. No. 6,560,139). The SRAM cell 100 includes PMOS transistors 102 and 104 serially coupled with NMOS transistors 106 and 108, respectively, between power supply nodes having an operating voltage CVDD and an NMOS transistor 110. When the cell 100 is being accessed, the NMOS transistor 110 is turned on to allow the transistors 102, 104, 106 and 108 to function properly. When the cell 100 is not being accessed, the NMOS transistor 110 is turned off for reducing the leakage current from the bit line or the power supply nodes (CVDD) to ground.
One drawback of the conventional SRAM cell 100 is that the NMOS transistor 110 may adversely affect the operation of the NMOS transistors 106 and 108. Conventionally, the NMOS transistors 106, 108 and 110 are constructed directly on the same P-type substrate. When a voltage is applied to the gate of the NMOS transistor 110, the bias between the substrate and the sources of the NMOS transistors 106 and 108 can be adversely affected. Thus, the NMOS transistor 110 may cause a reliability issue to the cell 100.
As such, what is needed is a SRAM device with a leakage current reduction feature, without causing reliability issues.